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| - 1 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc 128mbit gddr2 sdram revision 1.7 january 2003 1m x 32bit x 4 banks with differential data strobe and dll gddr2 sdram samsung electronics reserves the right to change products or specification without notice.
- 2 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc revision history revision 1.7 (january 23, 2003) - changed the device name from gddr-ii to gddr2 revision 1.6 (december 18, 2002) - typo corrected revision 1.5 (december 4, 2002) - typo corrected revision 1.4 (november 12, 2002) - changed the device name from ddr-ii to gddr-ii - typo corrected revision 1.3 (november 8, 2002) - typo corrected revision 1.2 (november 5, 2002) - typo corrected - changed the icc6 from 3ma to 7ma revision 1.1 (october 30, 2002) - typo corrected revision 1.0 (september 30, 2002) - changed tck(max) from 4.5ns to 4.0ns revision 0.7 (september 12, 2002) - added ibis curve in the spec - defined dc spec - typo corrected - defined burst write with ap (al=0) table. - defined on-die termination status of 2banks system table. - changed c in1 ,c in2 ,c in3 ,c out and c in4 from 3.5pf to 3.0pf - removed cl(cas latency) 8 from the spec - changed vdd form 2.5v + 5% to 2.5v + 0.1v - changed speed bin from 5 00/400/333mhz to 500/450/400mhz - changed emrs table revision 0.6 (february 28, 2002) - changed wl(write latency) from rl(read latency) -1 to al(additive latency) +1 - changed tih/tss during emrs from 5ns to 0.5tck - changed trcdwr - changed package ball location of ck, /ck, cke - 3 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc revision 0.5 (january 2002) - eliminated dllen pin - power-up sequence revision 0.4 (january 2002) - changed emrs table - changed self-refresh exit mode - changed on-die termination control - changed ocd control method - power-up sequence revision 0.3 (december 2001) - noted the ball names changed from ddr-1 and exchanged dqs and /dqs ball location. - added on-die termination control - changed ocd align mode entry / exit timing - added target value of data & dqs input/output capacitance(dq 0 ~dq 31 ) - added table for auto precharge control - typo corrected. revision 0.2 (november 2001) - data strobe scheme is changed from dqs separation of read dqs, write dqs to differential and bi-directional dqs - ocd adjustment - controlled dq is changed from dq0, wdqs2 to dq23, dqs2 and /dqs2 revision 0.1 (october 2001) - data strobe scheme is changed from bi-directional dqs to dqs separation to read dqs, write dqs - package ball layout is changed for mirror package. - ocd adjustment controlled dq is changed from dq0, dqs0 to dq23, wdqs2 - added dm descriptions - 1bank, 2bank system - added system selection mode in emrs table. revision 0.0 (august 2001) - 4 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc ? 2.5v + 0.1v power supply for device operation ? 1.8v + 0.1v power supply for i/o interface ? on-die termination for all inputs except cke,zq ? output driver strength adjustment by emrs ? sstl_18 compatible inputs/outputs ? 4 banks operation ? mrs cycle with address key programs - cas latency : 5, 6, 7 (clock) - burst length : 4 only - burst type : sequential only ? additive laten cy (al): 0,1(clock) ? read latency(rl) : cl+al ? write latency(wl) : al+1 general description features ? differential data strobes for data-in, date out ; - 4 dqs and /dqs(one di fferential strobe per byte) - single data strobes by emrs. ? edge aligned data & data strobe output ? center aligned data & data strobe input ? dm for write masking only ? auto & self refresh ? 32ms refresh period (4k cycle) (16ms is under consideration) ? 144 ball fbga ? maximum clock frequency up to 500mhz ? maximum data rate up to 1gbps/pin ? dll for address, cmd and outputs 1m x 32bit x 4 banks gddr2 synchr onous dram with differential data strobe ordering information part no. max freq. max data rate interface package K4N26323AE-gc20 500mhz 1000mbps/pin sstl_18 144 ball fbga K4N26323AE-gc22 450mhz 900mbps/pin K4N26323AE-gc25 400mhz 800mbps/pin the 4mx32 gddr2 is 134,217,728 bits of hyper synchronous data rate dynamic ram organized as 4 x 1,048,976 words by 32 bits, fabricated with samsung ?s high performance cmos technology. synchronous features with data strobe allow extremely high performance up to 4gb/s/ chip. i/o transactions are possible on both edges of the clock cycle. range of operating frequencies, and programmable latencies allow the devi ce to be useful for a variet y of high performance memory system applications. for 1m x 32bit x 4 bank gddr2 sdram - 5 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc pin configuration note : 1. rfu1 is reserved for a12 2. rfu2 is reserved for ba2 3. (m,13) vref for cmd and address 4. (m,2) vref for data input dq23 a3 vdd vss rfu 2 vdd vdd rfu 1 vss vdd a4 dq8 vref a2 a10 /ras nc cke nc zq /cs a9 a5 vref a0 a1 a11 ba0 /cas ck /ck /we ba1 a8/ap a6 a7 2345678910111213 b c d e f g h j k l m n dqs0 /dqs0 vssq dq3 dq2 dq0 dq31 dq29 dq28 vssq /dqs3 dqs3 dq4 dm0 vddq vddq dq1 vddq vddq dq30 vddq vddq dm3 dq27 dq6 dq5 vssq vssq vssq vdd vdd vssq vssq vssq dq26 dq25 dq7 vddq vdd vss vssq vss vss vssq vss vdd vddq dq24 dq17 dq16 vddq vssq vssq vddq dq15 dq14 nc, vss nc, vss nc, vss nc, vss dq19 dq18 vddq vssq vssq vddq dq13 dq12 nc, vss nc, vss nc, vss nc, vss dqs2 /dqs2 nc vssq vssq nc /dqs1 dqs1 nc, vss nc, vss nc, vss nc, vss dq20 dm2 vddq vssq vssq vddq dm1 dq11 nc, vss nc, vss nc, vss nc, vss dq21 dq22 vddq vssq vss vss vss vss vssq vddq dq9 dq10 normal package (top view) - 6 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc pin configuration mirror package (top view) dq23 a3 vdd vss rfu 2 vdd vdd rfu 1 vss vdd a4 dq8 vref a2 a10 /ras nc cke nc zq /cs a9 a5 vref a0 a1 a11 ba0 /cas ck /ck /we ba1 a8/ap a6 a7 2 3 4 5 6 7 8 9 10 11 12 13 b c d e f g h j k l m n dqs0 /dqs0 vssq dq3 dq2 dq0 dq31 dq29 dq28 vssq /dqs3 dqs3 dq4 dm0 vddq vddq dq1 vddq vddq dq30 vddq vddq dm3 dq27 dq6 dq5 vssq vssq vssq vdd vdd vssq vssq vssq dq26 dq25 dq7 vddq vdd vss vssq vss vss vssq vss vdd vddq dq24 dq17 dq16 vddq vssq vssq vddq dq15 dq14 nc, vss nc, vss nc, vss nc, vss dq19 dq18 vddq vssq vssq vddq dq13 dq12 nc, vss nc, vss nc, vss nc, vss dqs2 /dqs2 nc vssq vssq nc /dqs1 dqs1 nc, vss nc, vss nc, vss nc, vss dq20 dm2 vddq vssq vssq vddq dm1 dq11 nc, vss nc, vss nc, vss nc, vss dq21 dq22 vddq vssq vss vss vss vss vssq vddq dq9 dq10 * under consideration - 7 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc input/output functional description symbol type function ck, ck input clock: ck and ck are differential clock inputs. cmd, add i nputs are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to the crossings of ck and ck (both direc- tions of crossing). cke input clock enable: cke high activates, and cke low deactivates, internal clock signals and device input buffers and output drivers. taking cke low provides precharge power-down and self refresh operation (all banks idle), or active power-down (row active in any bank). c ke is synchronous for power down entry and exit, and for self refresh entry. cke is asynchronous fo r self refresh exit. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck and cke are disabled during powe r-down. input buffers, excluding cke, are disabled during self refresh. cs input chip select: all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. ras , cas , we input command inputs: ras , cas and we (along with cs ) define the command being entered. dm0 ~dm3 input input data mask: dm is an input mask signal fo r write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of clock. although dm pins are input only, the dm loading matches the dq and dqs loading. ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an acti ve, read, write or precharge command is being applied. ba0 also determines if the mode register or extended mode register is to be accessed during a mrs or emrs cycle. a0 - a11 input address inputs: provided the row address for active commands and the column address and auto precharge bit for read/write commands to select one location out of t he memory array in the respective bank. a8 is sampled during a precharge command to determine whether the pr echarge applies to one bank (a8 low) or all banks (a8 high). if only one bank is to be precharged, the bank is selected by ba0, ba1. the address inputs also provide the op-code during mode register set commands. dq input/ output data input/ output: bi-directional data bus. dqs0~ dqs3 dqs0 ~ dqs3 input/ output data strobe: output with read data, input with write data for source synchronous operation.edge-aligned with read data, centered in write data. dqs scheme differential dqs per byte dqs0, dqs0 dqs0 for dq0-dq7 dqs1, dqs1 dqs1 for dq8-dq15 dqs2, dqs2 dqs2 for dq16-dq23 dqs3, dqs3 dqs3 for dq24-dq31 nc/ rfu no connect: no internal electrical connection is present. v ddq supply dq power supply: 1.8v 0.1v v ssq supply dq ground v dd supply power supply: 2.5v 0.1v v ss supply ground v ref supply reference voltage: half vddq , 2 pins : (m,2) for data input , (m,13) for cmd and address zq input resistor connection pin for on-die termination. the value of resistor = 2 x (target value (rterm) of termination resistance of dq pin of each chip) - 8 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc block diagram (1mbit x 32i/o x 4 bank) bank select timing register address register refresh counter row buffer row decoder col. buffer data input register serial to parallel 1m x 32 1m x 32 1m x 32 1m x 32 sense amp 4-bit prefetch output buffer i/o control column decoder latency & burst length programming register strobe gen. ick addr lcke ick cke cs ras cas we dmi ldmi ck,ck lcas lras lcbr lwe lwcbr lras lcbr 128 32 32 lwe ldmi x32 dqi input buffer ck, ck 128 output dll * ick : internal clock input dll input buffer dqs, dqs dqs , dqs - 9 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc self auto idle mrs emrs row precharge power write power act read a read refs refsx refa ckel mrs ckeh ckeh ckel write power applied automatic sequence command sequence read a write a read pre pre pre pre refresh refresh down power down active on a read a read a write a preall active precharge precharge preall read write preall = precharge all banks mrs = mode register set emrs = extended mode register set refs = enter self refresh refsx = exit self refresh refa = auto refresh ckel = enter power down ckeh = exit power down act = active write a = write with autoprecharge read a = read with autoprecharge pre = precharge funtional description simplified state diagram dll enable write - 10 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc power-up sequence gddr2 sdrams must be powered up and initialized in a predefined manner to pre vent undefined operations. 1. power up sequence - apply power and keep cke at low state. (all other inputs may be undefined) - apply vdd before vddq. - apply vddq before vref. - start low frequency clock (100mhz) and maintain stable condition for minimum 200us. - the minimum of 200us after stable power and clock (ck, /ck), apply nop and take cke to be high. - issue precharge command for all banks of the device ( ts/th =0.5tck). - issue emrs command to initialize dram with dll off and on-die termination off( ts/th=0.5tck) . - issue emrs command to control dll and decide on-die termination state. within 100 clocks after issu ing emrs command for dll on, stable high frequency clock should be supplied to dram. (v=valid value) - the additional 1ms clock cycles ar e required to lock the dll and determine value of on-d ie termination after issuing emrs command or supply ing stable clock fr om a controller. apply nop during locking dll to protect invalid command. - issue precharge command for all banks of the device. - issue emrs command - issue at least 10 or more auto refresh command to update the value of on-die termination. - issue a mrs command to initialize the mode register. - issue any command. power up & initialization sequence cmd trp ck, ck ~ ~ cke precharge nop 1st auto refresh 10th auto refresh trfc mrs 4 clock min. any command 1ms 200 us emrs 2 < 100tck all banks stable high freq. nop * minimum setup/hold time tis, tihmin = 0.5tck at the low frequency without dll * within 100 tck after issuing emrs2, p ll(dll) of controller should be enabled. * during changing clock frequency, the changi ng rate should be smaller than 100ps/30tck low freq. (> 100mhz) emrs 1 nop nop emrs precharge all banks trp tmrd address bus ba 1 ba 0 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 010 x x 0 x 00 x extended mode register address bus ba 1 ba 0 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 010 v v 1 v vv v extended mode register trfc - 11 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc 0 the mode register stores the data for controlling the va rious operating modes of gddr 2 sdram. it programs cas latency, addressing mode, test mode and various vendor spec ific options to make gddr2 s dram useful for variety of dif- ferent applications. the default value of the mode register is not defined, therefore the mode register must be written after emrs setting for proper operation. the mode register is written by asserting low on cs , ras , cas and we (the gddr2 sdram should be in active mode with cke already high prior to writing into the mode register). the state of address pins a 0 ~ a 11 and ba 0 , ba 1 in the same cycle as cs , ras , cas and we going low is written in the mode register. minimum four clock cycles are requested to comple te the write operation in the mode regist er. the mode register contents can be changed using the same command and clock cycle requirem ents during operation as long as all banks are in the idle state. the mode register is divided into various fields depending on functionality. the burst length uses a 0 ~ a 2 , addressing mode uses a 3 , cas latency (read latency fr om column address) uses a 4 ~ a 6 . a 7 is used for test mode. a 9 ~ a 11 are used for twr. refer to the table for specific codes for various addressing modes and cas latencies. mode register set(mrs) address bus mode register cas latency a 6 a 5 a 4 latency 000 reserved 0 0 1 reserved 0 1 0 reserved 0 1 1 reserved 1 0 0 reserved 101 5 110 6 111 7 twr a 11 a 10 a 9 mrs select 0 0 0 reserved 0 0 1 reserved 010 3 011 4 100 5 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved *1. bl 4, sequential only ba 1 ba 0 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 0twr 0 tm cas latency bt burst length test mode a 7 mode 0 normal 1test burst length a 2 a 1 a 0 burst length 010 4 burst type a 3 burst type 0 sequential ba 0 a n ~ a 0 0mrs 1emrs * *1 - 12 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc output driver strength option a 9 a 8 a 7 ron[ohm] 000 60 001 55 010 50 011 45 100 40 101 35 110 30 111 25 the extended mode register stores the data output driver strength and on-die termination options. the extended mode register is written by asserting low on cs , ras , cas , we and high on ba0(the gddr2 sdram should be in all bank precharge with cke already high prior to writing into the extended mode regis- ter). the state of address pins a0 ~ a11 and ba0 in the same cycle as cs , ras , cas and we going low are written in the extended mode register. four clock cycles are required to complete the write operation in the extended mode register. 8 kinds of the output driver strength are supported by emrs (a9, a8, a7) code. the mode register contents can be changed using the same command and clock cycle requirements during opera- tion as long as all banks are in the idle state. "high" on ba0 is used for emrs. refer to the table for specific codes. dll a 6 dll 0 dlloff 1dllon extended mode register set(emrs) address bus extended ba 1 ba 0 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 1 0 odt.r output driver strength dll dqs a.l odt control odt option mode register off : on-die termination of cmd and addr pins on dram is off x1 : on-die termi nation value of cmd and add pins are same as the value of dq x2 : 2 times of the value of dq x4 : 4 times of the value of dq on-die termina tion option for cmd & addr a 1 a 0 value 00 off 01 x1 10 x2 11 x4 odt of dqs @ rd a 10 mode 0on 1off ba 0 a n ~ a 0 0mrs 1emrs on-die termination mode a 3 a 2 value 0 0 odt off 0 1 odt cal. on 1 0 rterm=60 1 1 rterm=120 *1. dll control,odt control,and odt option command should be issued at low frequency clock( <100mhz) with tis/tih=0.5tck *1 *1 additive latency a 4 latency 00 11 *2 *2. when single dqs is selected, 4 /dqs pins should be connected to vref. *1 dqs a 5 dqs 0differential 1single - 13 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc dqs 012345 ck, ck dqs dq differntial dqs timing (cl5, bl4) 6789101112 13 14 15 16 17 18 19 20 cmd dqs read write 012345 single dqs timing (cl5, bl4) 6789101112 13 14 15 16 17 18 19 20 read write vref level dout0 dout1 dout2 dout3 din0 din1 din2 din3 dout0 dout1 dout2 dout3 din0 din1 din2 din3 * to support existing ddr-i user , single dqs is supported under 400mhz by emrs option, when single dqs is selected, 4 /dqs pins should be connected to vref. 500mhz 450mhz 400mhz differential dqs differential dqs differential dqs single dqs ck, ck dqs dq cmd dqs - 14 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc bank activate command the bank activate command is issued by holding cas and we high with cs and ras low at the rising edge of the clock. the bank addresses ba0 and ba1 are used to select the desired bank. the row address a0 through a11 is used to deter- mine which row to activate in the selected bank. the bank activate command must be applied before any read or write operation can be executed. immediately after the bank active command, the gddr2 sdram can accept a read or write command on the foll owing clock cycle. if a r/w command is issued to a bank that has not satisf ied the trcdmin specifi- cation, then additive latency mu st be programmed into the device to delay wh en the r/w command is internally issued to the device. the additive latency value must be chosen to assure trcdmin is satisfied. additive latencies of (0,1) are supported. once a bank ha s been activated it must be precharged before another bank activate command can be applied to the same bank. the bank active and precharge times are defined as tras and trp, respectively. the minimu m time interval between successi ve bank activate commands to the same bank is determined by the ras cycle time of the device (t rc ), which is equal to tras + trp. the minimum time interval between bank acti- vate commands, bank 0,1, 2, 3 (in any order), is the bank to bank delay time (t rrd ). 012345 131415161718 9 t rrd = 5 27 additive latency cas latency t ras = 19 internal read command start (bank a) internal read command start (bank b) ck, ck cmd dqs bank a activate post cas read a bank b activate post cas read b bank a activate 8 bank b precharge t rcd = 9 bank activate command cycle : cl=7, t rcd =9, al=1, t rp =8, t rrd =5, t ccd =2, t ras =19 read and write access modes after a bank has been activated, a re ad or write cycle can be executed. th is is accomplished by setting ras high, cs and cas low at the clock?s rising edge. the we must also be defined at this time to determine whether the access cycle is a read operation (we high) or a write operation (we low). a new burst access must not interrupt the previous 4 bit burst operation. the minimum cas to cas delay is defined by tccd, and is a minimum of 2 cl ocks for read or write cycles. write latency the write latency(wl) is always defined as al(additive latency)+1 where read latency is defined as the sum of addi- tive latency plus cas latency (rl=al+cl). bank a precharge 24 additive latency 19 t rp = 8 dout0 dout1 dou2 dout3 dq - 15 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc posted cas posted cas operation is supported to make command and data bus efficient for sustainable bandwidths in gddr2 sdram. in this operation, the gddr2 sdram allows a cas read or write command to be issued trcdmin or 1 tck ear- lier than trcdmin after the ras bank activate command. the command is held for the time of the additive latency (al) before it is issued inside the device. the read latency (rl) is controlled by the sum of al and the cas latency (cl). therefore if a user chooses to issue a r/w command before the trcdmin, then al (greater than 0) must be written into the emrs. examples of posted cas operation example 1 read followed by a write to the same bank [al = 1, t rcd = 9, cl = 7, rl = (al + cl) = 8, wl = (al + 1) = 2] example 2 read followed by a write to the same bank [al = 0, t rcd = 9, cl = 7, rl = (al + cl) = 7, wl = (al + 1) = 1] 0 7 8 151617181920 13 cmd dqs dq 21 ck, ck 0 1 8 14151617181920 9 cmd dqs dq 21 ck, ck t rl dout0 dout1 dou2 dout3 din0 din1 din2 din3 din0 din1 din2 din3 read a-bank active a-bank read a-bank 22 active a-bank dout0 dout1 dout2 dout3 14 23 22 t hz thz > 1 tck t rcd rl write a-bank t wl write a-bank t wl - 16 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc burst read command the burst read command is initiated by having cs and cas low while holding ras and we high at the rising edge of the clock. the address inputs determine the starting column addre ss for the burst. the delay from the start of the command to when the data from the first cell appears on the outputs is e qual to the value of the read latency (rl). the data strobe out- put (dqs) is driven low 1 clock before valid data (dq) is driv en onto the data bus. the first bit of the burst is synchronized with the rising edge of the data strobe (dqs). each subseq uent data-out appears on the dq pin in phase with the dqs signal in a source synchronous manner. the rl is equal to an additive latency (al) plus cas latency (cl). the cl is defined by the mode register set (mrs), similar to the existing sdr and ddr-i sdrams. the al is defined by the extended mode register set (emrs). cmd dqs ck, ck rl = 7 dqs nop post cas nop nop nop nop read a posted cas nop nop nop nop tdqsck read a internal read command start (bank a) burst read operation: rl = 7 (al = 0 and cl = 7) al =1 cl = 7 rl = 8 02 1 7 8 9 10 11 12 13 nop post cas nop nop nop read a posted cas nop nop nop nop tdqsck read a burst read operation: rl = 8 (al = 1, cl = 7) cmd dqs ck, ck dqs internal read command start (bank a) cl = 7 douta 0 douta 1 douta 2 douta 3 douta 4 douta 5 douta 6 douta 7 douta 0 douta 1 douta 2 douta 3 douta 4 douta 5 douta 6 douta 7 02 1 7 8 9 10 11 12 13 - 17 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc nop burst read followed by burst write : al = 1, cl = 7, rl = 8, wl = (al+1) = 2 the seamless burst read operation is supported by enabling a read command at every other clock. this operation is allowed regardless of same or different banks as long as the banks are activated. cmd nop nop nop nop nop dq?s nop ck, ck 02 1 7 8 9 10 11 read a0 post cas al = 1 cl =7 rl = 8 dqs read a4 post cas seamless burst read operation: cl = 7, al = 1, rl = 8 cmd post cas nop nop dq?s nop ck, ck 06 189101112 dqs read a wl = 2 rl =8 nop nop nop 7 thz douta 0 douta 0 douta 1 douta 2 douta 3 dina 0 dina 1 dina 2 dina 3 nop thz > 1 tck post cas write a nop douta 1 douta 2 douta 3 douta 4 douta 6 douta 5 13 - 18 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc burst write operation the burst write command is initiated by having cs , cas and we low while holding ras high at the rising edge of the clock. the address inputs determine the starting column address. write latency (wl) is defined by an additive latency(al) plus one and is equal to (al + 1). the first data bit of the burst cycle mu st be applied to t he dq pins at the first rising edge of the clock and at the first falling edge of the clock. the tdqss specificati on must be satisfied for write cycles. the subsequent burs t bit data are issued on successi ve edges of the cl ock until the burst length of 4 is com- pleted. when the burst has finished, any additional data su pplied to the dq pins will be ignored. the dq signal is ignored after the burst write operation is complete. the time from the completion of the burst write to bank precharge is the write recovery time (twr). burst write operation : al= 1, cl = 7, wl = 2 , t wr = 5 cmd posted cas nop nop nop nop nop dq nop ck, ck 1 023456 9 wl =2 precharge write a cmd dq ck, ck dqs cl = 7 twl = 1 burst write followed by burst read : rl = 7 (al=0, cl=7), wl = 1 , tcdlr = 4 the minimum number of clock from the burst write co mmand to the burst read comma nd is wl+2+a write-to- read-turn-around-time(tcdlr). 023 141516 nop nop nop nop nop nop nop post cas read a write to read latency = wl + 2 + t cdlr =7 nop > = tcdlr dina 0 dina 1 dina 2 dina 3 dina 0 dina 1 dina 2 dina 3 douta 0 douta 1 douta 2 douta 3 dqs post cas write a 1 7 nop twr = 5 - 19 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc seamless burst write operation : al = 1, cl = 7, wl = al + 1 = 2 the seamless burst write operation is supported by enabling a write command every other clock. this operation is allowed regardless of same or different banks as long as the banks are activated dq?s ck, ck 02 137891011 wl = 2 dqs cmd nop nop nop nop nop nop nop write a post cas write b post cas dina 0 dina 1 dina 2 dina 3 dinb 0 dinb 1 dinb 2 dinb 3 - 20 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc precharge command the precharge command is used to precharge or close a bank that has been activated. the precharge command is triggered when cs , ras and we are low and cas is high at the rising edge of the clock. the precharge command can be used to precharge each bank independently or all banks simultaneously. three address bits a8, ba0 and ba1 are used to define which bank to precharge when the command is issued. bank selection for precharge by address bits burst read operation followed by precharge for the earliest possible precharge, the precharge command may be issued on the rising edge which is cas latency (cl) clock cycles before the end of the re ad burst. a new bank acti ve (command) may be issued to the same bank after the ras precharge time (t rp ). a precharge command cannot be issued until t ras is satisfied. a8 ba1 ba0 precharged bank(s) low low low bank 0 only low low high bank 1 only low high low bank 2 only low high high bank 3 only high don?t care don?t care all banks 0 ~ 3 cl =7 burst read operation followed by precharge: rl = 7 (al=0, cl=7), t rp = 8 03 2 56789 10 11 precharge nop nop nop nop nop active bank a nop nop dq ck, ck dqs cmd read a post cas 4 > = t rp nop douta 0 douta 1 douta 2 douta 3 - 21 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc burst read operation followed by precharge: rl = 8 (al=1, cl=7, t rp =8) burst write followed by precharge: al = 1, cl = 7, wl = al + 1 = 2, t wr = 5 cmd nop nop nop nop nop nop dq?s nop ck, ck 02 1 3456 9 write a posted cas wl = 2 precharge a t wr = 5 burst write followed by precharge for write cycles, a delay must be satisf ied from the comple tion of the last bu rst write cycle until the precharge command can be issued. this delay is known as a write recovery time (t wr ) referenced from the completi on of the burst write to the precharge command. no precharge command should be issued prior to the twr delay, as gddr2 sdram does not sup- port any burst interrupt operation. cmd dq?s ck, ck rl = 8 dqs > = t rp 0 3 78910111213 precharge a nop read a posted cas nop nop nop bank a activate nop nop douta 0 douta 1 douta 2 douta 3 dina 0 dina 1 dina 2 dina 3 dqs - 22 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc auto-precharge operation before a new row in an active bank can be opened, the active bank must be precharged using either the precharge command or the auto-precharge function. when a read or a write command is given to the gddr2 sdram, the cas timing accepts one extra address, column address a8, to allo w the active bank to automatically begin precharge at the earliest possible moment during the bu rst read or write cycle. if a8 is low when the read or write command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst sequence. if a8 is high when the read or write comma nd is issued, then the auto-precharge function is engaged. this feature allows the precharge operat ion to be partia lly or completely hidden duri ng burst read cycles (dependent upon cas latency) thus improving system pe rformance for random data access. the ras lockout circuit internally delays the precharge operation until the array restore oper ation has been completed so that the auto precharge com- mand may be issued with any read or write command. auto-precharge also be implemented during write commands . the precharge operation engaged by the auto precharge command will not begin until the last data of the burst wr ite sequence is properly stored in the memory array. the ddr sdram has a data mask function that can be used in conjunction with data wr ite cycle only, not read cycle. when the data mask is activated (dm high) during write oper ation the write data is maske d immediately (dm to data-mask latency is zero). dm must be issued at the rising edge or the fall ing edge of data strobe instead of a clock edge. dm function dm masked by dm=h cmd nop nop nop nop nop nop dq?s nop ck, ck 02 1 3456 9 write a posted cas precharge a t wr = 5 dina 0 dina 2 dina 3 dqs dina1 wl = 2 - 23 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc burst read with auto precharge followed by same bank activation : rl = 8 (al = 1, cl = 7, internal t rp = 8) cmd nop nop nop nop nop dq?s nop ck, ck 037891011 read a post cas rl = 8 dqs > = t rp a8 = 1 nop 12 activate bank a nop auto precharge begins douta 0 burst read with auto precharge (al=0) *when al(additive latency) is 1, a precharge command for same bank can be issued at 3th cycle only and others are same with al=0. asserted command for same bank for different bank 1 2 3 4 1 2 3 4 read illegal legal illegal illegal illegal legal legal legal read with auto precharge illegal legal illegal illegal illegal legal legal legal active illegal illegal illegal illegal legal legal legal legal precharge illegal legal illegal illegal legal legal legal legal burst read with auto precharge if a8 is high when a read command is issued, the read with auto-precharge function is engaged. the gddr2 sdram starts an auto prechar ge operation on the rising edge which is (al + bl/2)cycles later from the read with auto precharge command, when tras(min) is satisfied. if tras(min) is not satisfied at the edge, the start point of auto pre- charge operation will be delayed until tras(min) is satisfied. a new bank active command may be issued to the same bank if the following two conditions are satisfied simultaneously. (1) the ras precharge time (trp) has been satisfied from the clock at which the auto precharge begins. (2) the ras cycle time (trc) from the prev ious bank activation has been satisfied. when the read with auto-precharge command is issued, new command (read, read with auto precharge or pre- charge) of same bank can be asse rted tccd=2 clock cycles later. douta 1 douta 2 douta 3 - 24 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc burst write with auto-precharge : al = 0, wl = 1, t wr = 5, t rp =8(for the same bank) cmd nop nop nop nop nop bank a dqs nop ck, ck 0 2 3478916 write a post cas a8 = 1 nop > = t wr active > = t rp dina 0 dina 1 dina 2 dina 3 dqs auto precharge begins wl=1 burst write with auto-precharge if a8 is high when a write command is issued, the write with auto-precharge function is engaged. the gddr2 sdram automatically begins precharge operation after the completi on of the burst write plus write recovery time (twr). interruption of the write with auto-precharge function is prohibited. active command of same bank can be issued wl+twr+trp+bl/ 2 cycles later from the write with auto-prech arge command. the bank undergoing auto-precharge from the completion of the write burst may be reactiva ted if the following two co nditions are satisfied. (1) the data-in to bank activate delay time (twr + trp) has been satisfied. (2) the ras cycle time (trc) from the prev ious bank activation has been satisfied. burst write with auto-precharge (al=0) *when al(additive latency) is 1, a active command for same bank c an be issued from 17th cycle , a read or read with auto pre- charge command for different bank can be issued from 8th cycle and others are same with al=0. * all bank precharge command can be issued from 8th cycle. asserted command for same bank for different bank 1 ~ 7 8 9 ~ 15 16 1 2 ~ 6 7 write illegal illegal illegal illegal illegal legal legal write with auto precharge illegal illegal illegal illegal illegal legal legal read illegal illegal illegal illegal illegal illegal legal read with auto precharge illegal illegal illegal illegal illegal illegal legal active illegal illegal illegal legal legal legal legal precharge illegal illegal illegal illegal legal legal legal all bank precharge illegal legal legal legal - 1 - 25 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc self refresh command the gddr2 sdram device has a bui lt-in timer to accommodate self refresh operat ion. the self refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock. once the self refresh command is registered, cke must be held low to keep the device in self refresh mode and nop command should be issued or cs should be held high to ensure stable self refresh operation for next four cycles after the self refresh command. when the gddr2 sdram has entered self refresh mode all of the external control si gnals, except cke, are disabled. the clock is internally disabled during self refres h operation to save power. the user may halt the external clock wh ile the device is in self refr esh mode, however, the clock must be restarted before the device can exit self re fresh operation. after cke is brought high, an internal timer is started to insure cke is held high for approximately 10ns before register ing the self refresh exit command. the pur pose of this circuit is to filter out noise glitches on the cke input which may cause the gddr2 sdram to erroneousl y exit self refresh operati on. once the self refresh exit command is registered, a delay equal or longer than the txsa (>20000 tck) must be satisfied before any command can be issu ed to the device. cke must remain high fo r the entire self refresh exit period (t xsa > 20000tck) and commands must be gated off wi th cs held high. alternatively, nop commands may be registered on eac h positive clock edge during the se lf refresh exit interval. (s ee figure.) cmd ck, ck cke self refresh any command txsa (> 20000tck) *after self refresh entry, nop or chip deselect command should be issued during more than 4 cycles automatic refresh command (cas before ras refresh) when cs , ras and cas are held low and we high at the rising edge of the clock, the chip enters the automatic refresh mode (cbr). all banks of the gddr2 sdram must be prec harged and idle for a minimum of the precharge time (t rp ) before the auto refresh command (cbr) can be applied. an address counter, internal to the device, supplies the bank address during the refresh cycle. no cont rol of the external address bus is re quired once this cycle has started. when the refresh cycle has completed, all banks of the gddr2 sdram will be in t he precharged (idle) state. a delay between the auto refresh command (cbr) and the next ac tivate command or subsequent auto refresh command must be greater than or equal to the auto refresh cycle time (t rfc ). ck, ck cmd cbr bank nop nop precharge cke nop > = t rp > = t rfc high activate and chip deselet command should be issued for txsa after self refresh exit. > = 4clk nop nop - 26 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc power-down power-down is entered when cke is registered low (no acce sses can be in progress). if po wer-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and output buffers, excluding ck, ck and cke. during 4 cycles afte r power down mode issued, nop should be issued or cs must be held high. in power down mode, cke low and a stable clock signal must be maintained at the inputs of the gddr2 sdram, and all other input si gnals are ?don?t care? except first 4 cycles after power down mode i ssued. power-down duration is limited by the refr esh requirements of the device. the power-down state is synchronously exited when cke is registered high (along with a nop or cs hold high). a valid, executable command may be ap plied four clock cycles later. power down nop t is t is ck, ck cke cmd no column access in progress valid nop *1 valid don?t care enter power down mode ( read or write operation must not be in progress) nop exit power down mode 4tck nop nop nop nop *1. nop or cs held high should be issued more than 4 cycles. burst interruption interruption of a burst read or write cycle is prohibited. no operation command the no operation command should be used in cases when the gddr2 sdram is in an idle or a wait state. the pur- pose of the no operation command is to prevent th e gddr2 sdram from registering any unwanted commands between operations. a no operation command is registered when cs is low with ras , cas , and we held high at the rising edge of the clock. a no operation command will not termi nate a previous operation that is still executing, such as a burst read or write cycle. the desele ct command performs the same function as a no operation command. deselect command occurs when cs is brought high at the rising edge of the clock, the ras , cas , and we signals become don?t cares. *cl + 2tck after read or cl after last data in, a power-down command can be issued. - 27 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc on-die termination all pins except zq, cke pins adopt on-die termination to improve signal integrity of channel. the on-die termination should be controlled by emrs command at low frequency clock (<100mhz). the on-die termination control command should be issued before i ssuing dllon command by emrs or simultaneous ly to guarantee stable channel condition of /ck and ck pins. if a3, a2 = 0, 0, the on-die termination of all pins will be deactivated. if a3, a2 = 0, 1, the on-die termination will be self-calibrated by detecting the external resist or on zq pin. if a3, a2 = 1, 0, the value of the on-die termination of ck, /ck, 32 dq?s, 4 dm?s, 4 /dqs?s and 4dqs pins will be the fixed value, 6 0ohm. if a3, a2 = 1, 1, the value of the on-die termination of ck, /ck, 32 dq?s, 4 dm?s, 4 /dqs?s and 4dqs pins will be the fixed value,120ohm. if a3, a2 = 0, 1 is issued by emrs, the value of the on-d ie termination of each pin is determined by monitoring the value of a external resistor which is connected between zq pin and vssq, and updated every cbr refresh cycle to compensate variation of voltage and temperature. the value of on-die termination of cmd and add (/ras, /cas, /we, /cs, ba0 , ba1 and a0 ~ a11) pins of each dram depend on emrs code (a1, a0). if a1, a0 = 0, 0 , the on-die termination of cmd and add pins will be deacti- vated. if a1, a0 = 0, 1, the value of the on-die termination of cmd and add pins will be same value as the value of dq pins. if a1, a0 = 1, 0, the value of the on-die termi nation of cmd and add pins will be two times of the value of dq pins. if a1, a0 = 1, 1, the value of the on-die terminati on of cmd and add pins will be four times of the value of dq pins. the on-die termination for one bank system with self-calibration code (a3, a2 = 0, 1) the value of external resistor (rref) at external one bank syst em is 2 times of target termi nation value of dq?s on chan- nel (rterm). then the value of on-die termination of ck, /ck, 32 dq?s, 4 dm?s, 4 /dqs ?s and 4dqs pins is half value of the external resistor. the value of on-die terminatio n of cmd and add ( /ras, /cas, /we, /c s, ba0, ba1 and a0 ~ a11) pins of each dram depend on emrs code (a2, a0). the following figure show s the typical external one bank system having on-die termination. block diagram of 1 bank system ck,/ck add /ras,/cas,/we,/cs dm?s, dq?s, dqs?s,/dqs?s ck,/ck dm?s, dq?s, dqs?s,/dqs?s ck,/ck /cs /ras,/cas,/we dm?s, dq?s, dqs?s,/dqs?s ck,/ck dm?s, dq?s, dqs?s,/dqs?s ck,/ck add /ras,/cas,/we,/cs dm?s, dq?s, dqs?s,/dqs?s zq front side drams controller rref=2 x rterm 2xrterm where rterm is the termination value on charnnel vssq vssq 2xrterm vssq ck,/ck add /ras,/cas,/we,/cs dm?s, dq?s, dqs?s,/dqs?s zq ck,/ck add /ras,/cas,/we,/cs dm?s, dq?s, dqs?s,/dqs?s zq 2xrterm vssq ck,/ck add /ras,/cas,/we,/cs dm?s, dq?s, dqs?s,/dqs?s zq - 28 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc the on-die termination on/off status on dram is in accompany with dram operation mode. power consumption by on-die termination can be reduced by issuing power down mode. * a10 in emrs code is used for on-die termi nation of dq?s off when read data comes out mode pin odt of dram self_refresh all off power down ck, /ck on other pins off active all on all banks idle ck, /ck, add?s, cmd on dq?s, dqs?s, /dqs?s, dm?s on read a10=1 ck, /ck, add?s, cmd, dm,s on dq?s, dqs?s, /dqs?s off a10=0 ck, /ck, add?s, cmd, dm,s on dq?s, dqs?s, /dqs?s on on-die termination (odt) status of 1 bank system - 29 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc . the on-die termination for external two bank system with self-calibration code (a3, a2 = 0, 1) the external resistor (rref) is equal to 2x the number of shared dram?s on one channel x target termination value of dq channel. the following figu re is represented the typical two bank system having on-die termination . 4 dram?s share one channel for cmd and add pins and 2 dram?s share one channel fo r dq?s and clk pins. the exte rnal resistor (rref) is 4 times of target termination value on channel. the on-die te rmination value of ck, /ck, 32 dq?s, 4 dm?s, 4 /dqs?s and 4dqs pins on channel is half value of the external resistor (rref). self-refresh and power do wn mode in two bank system shou ld be issued for all dram?s at the same time to keep suit- able on-die termination condition on channel. vssq vssq vssq vssq 1. with these case, the system couldn?t have suitable rterm. because the on-die termina tion value on channel is two times than the target value. mode pin dram remarks m1 m2 m1 m2 self_refresh self_refresh all off off self_refresh other states all illegal power down power down ck,/ck on on other pins off off power down other states illegal all banks idle active ck, /ck, add?s, cmd on on dq?s, dqs?s, /dqs?s, dm?s on on read a10=1 ck, /ck, add?s, cmd on on dq?s, dqs?s, /dqs?s, dm?s on off a10=0 ck, /ck, add?s, cmd on on dq?s, dqs?s, /dqs?s, dm?s on on active read a10=1 ck, /ck, add?s, cmd on on dq?s, dqs?s, /dqs?s, dm?s on off a10=0 ck, /ck, add?s, cmd on on dq?s, dqs?s, /dqs?s, dm?s on on *1 *1 block diagram of 2 banks system ck, /ck add /ras, /cas, /we, /cs dm?s, dq?s, dqs?s, /dqs?s ck, /ck dm?s, dq?s, dqs?s, /dqs?s ck, /ck dm?s, dq?s, dqs?s, /dqs?s ck, /ck dm?s, dq?s, dqs?s, /dqs?s controller ck, /ck add /ras, /cas, /we, /cs dm?s, dq?s, dqs?s, /dqs?s ck, /ck dm?s, dq?s, dqs?s, /dqs?s ck, /ck /cs /ras, /cas, /we, /cs dm?s, dq?s, dqs?s, /dqs?s ck, /ck dm?s, dq?s, dqs?s, /dqs?s ck, /ck add /ras, /cas, /we, /cs dm?s, dq?s, dqs?s, /dqs?s ck, /ck dm?s, dq?s, dqs?s, /dqs?s ck, /ck dm?s, dq?s, dqs?s, /dqs?s ck, /ck dm?s, dq?s, dqs?s, /dqs?s front side dram?s back side dram?s zq rref = 4 x rterm zq 4 x rterm zq 4 x rterm zq 4 x rterm zq 4 x rterm zq 4 x rterm zq 4 x rterm zq 4 x rterm add /ras, /cas, /we, /cs add /ras, /cas, /we, /cs add /ras, /cas, /we, /cs add /ras, /cas, /we, /cs add /ras, /cas, /we, /cs add /ras, /cas, /we, /cs - 30 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc 4. command truth table. (v=valid, x=don?t care, h=logic high, l=logic low) function cke cs ras cas we dm ba0/ba1 a11 - a9 a8 a7 - a0 notes previous cycle current cycle mode register set h x l l l l x ba0 = 0 and mrs op code 1 extended mode register set h x l l l l x ba0 = 1 and emrs op code 1 auto (cbr) refresh h h l l l h x x x x x 1 entry self refresh h l l l l h x x x x x 1 exit self refresh lhhxxxxxxxx1 lhlhhhxxxxx single bank precharge h x l l h l x ba x l x 1,2 precharge all banks h x l l h l x x x h x 1 bank activate h x l l h h x ba row address 1,2 write h x l h l l x ba x l column 1,2,3, write with auto precharge h x l h l l x ba x h column 1,2,3, read h x l h l h x ba x l column 1,2,3 read with auto-precharge h x l h l h x ba x h column 1,2,3 dm h x x x x x dm x x x x 6 no operation hxlhhhxxxxx1 hxhxxxxxxxx1 power down mode entry h l h x x x x x x x x 1,4,5 hllhhhxxxxx power down mode exit l h h x x x x x x x x 1,4,5 lhlhhhxxxxx 1. all of the gddr2 sdram operatio ns are defined by states of cs , we , ras , and cas at the positive rising edge of the clock. 2. bank select (ba0,1), determine which bank is to be operated upon. 3. burst read or write cycle may not be terminated. 4. the power down mode does not perform any refresh operations, t herefore the device can?t remain in this mode longer than the r efresh period (t ref ) of the device. four clock delay is required for mode entry and exit. 5. if cs is low, then when cke returns high, no command is registered into the chip for one clock cycle. 6. dm sampled at the rising and falling edges of the dqs and da ta-in are masked at the both edges (write dm latency is 0). - 31 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc 5. clock enable (cke) truth table current state cke command action notes previous cycle current cycle cs ras cas we ba1, ba0, a11 - a0 self refresh h x xxxx x invalid 1 l h h x x x x exit self refresh with device deselect 2 l h l h h h x exit self refresh with no operation 2 l h l command address illegal 2 l l xxxx x maintain self refresh power down h x xxxx x invalid 1 l h h x x x x power down mode exit, all banks idle 2 l h l h h h x exit power down mode with no operation 2 l h l command address illegal 2 l l xxxx x maintain power down mode all banks idle h h h x x x device deselect 3 h h l command address refer to the current state truth table 3 h l h x x x power down hll command except self- refresh command x illegal h l l l l h x entry self refresh 4 any state other than listed above h h xxxx x refer to operations in the current state truth table h l xxxx x power down 5 l h xxxx x power down l l xxxx x power down 1. for the given current state cke must be low in the previous cycle. 2. when cke has a low to high transition, the clock and other inpu ts are re-enabled asynchronously. the minimum setup time for c ke (t ces ) must be satisfied before any command other than self refresh exit. 3. the inputs (ba1, ba0, a11 - a0) depend on the command that is issued. see the current state truth table for more information. 4. the auto refresh, self refresh mode, and the mode register set modes can only be entered from the all banks idle state. 5. must be a legal command as defined in the current state truth table. - 32 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restri cted to recommended operating condition. exposure to higher than recommended voltage for extended per iods of time could affect device reliability. note : power & dc operating conditions(sstl_18 in/out) recommended operating conditions (voltage referenced to v ss =0v, t j =0 to 100 c) parameter symbol min typ max unit note device supply voltage v dd 2.4 2.5 2.6 v 1 output supply voltage v ddq 1.7 1.8 1.9 v 1 reference voltage v ref 0.49*v ddq - 0.51*v ddq v2 dc input logic high voltage v ih (dc) v ref +0.125 - v ddq +0.30 v 4 dc input logic low voltage v il (dc) -0.30 - v ref -0.125 v 5 ac input logic high voltage v ih(ac) v ref +0.25 - - v ac input logic low voltage v il(ac) --v ref -0.25 v output logic high voltage v oh vtt+0.4 - - v 6 output logic low voltage v ol --vtt-0.4v 6 input leakage current i il -5 - 5 ua 7 output leakage current i ol -5 - 5 ua 7 1. under all conditions v ddq must be less than or equal to v dd . 2. v ref is expected to equal 0.50*v ddq of the transmitting device and to track variations in the dc le vel of the same. peak to peak noise on the v ref may not exceed + 2% of the dc value. thus, from 0.50*v ddq , v ref is allowed + 25mv for dc error and an additional + 25mv for ac noise. 3. v tt of the transmitting device must track v ref of the receiving device. 4. v ih (max.)= v ddq +1.5v for a pulse and it which can not be greater than 1/3 of the cycle rate. 5. v il (mim.)= -1.5v for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. output logic high voltage and low voltage is depend on channel condition.(ract , ron) 7. for any pin under test input of 0v < v in < v dd is acceptable. for all other pins that are not under test v in =0v note : absolute maximum ratings parameter symbol value unit voltage on any pin relative to vss v in , v out -0.5 ~ 3.6 v voltage on v dd supply relative to vss v dd -1.0 ~ 3.6 v voltage on v dd supply relative to vss v ddq -0.5 ~ 3.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 4.5 w short circuit current i os 50 ma - 33 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc ac input operating conditions recommended operating conditions (voltage referenced to v ss =0v, v dd =2.5v 0.1v, v ddq =1.8v 0.1v, t j =0 to 100 c) parameter symbol min typ max unit note input high (logic 1) voltage; dq v ih v ref +0.25 - - v 1 input low (logic 0) voltage; dq v il --v ref -0.25 v 2 clock input differential voltage ; ck and ck v id 0.5 - v ddq +0.6 v 3 clock input crossing point voltage ; ck and ck v ix 0.5*v ddq -0.2 - 0.5*v ddq +0.2 v 4 1. v ih (max) = 4.2v. the overshoot vo ltage duration is < 3ns at vdd. v ih level should be met at the pin of dram when odt=on. 2. v il (min) = -1.5v. the undershoot vo ltage duration is < 3ns at vss. v il level should be met at the pin of dram when odt=on. 3. v id is the magnitude of the diff erence between the input level on ck and the input level on ck 4. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track va riations in the dc level of the same note : dc characteristics note : 1. measured with outputs open & on-die termination off. 2. refresh period is 16ms. parameter symbol test condition version unit note -20 -22 -25 operating current (one bank active) i cc1 burst lenth=4 t rc t rc (min) i ol =0ma, t cc = t cc (min) 590 540 500 ma 1 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = t cc (min) 110 100 95 ma precharge standby current in non power-down mode i cc2 n cke v ih (min), cs v ih (min), t cc = t cc (min) 230 210 190 ma active standby current power-down mode i cc3 p cke v il (max), t cc = t cc (min) 110 100 95 ma active standby current in in non power-down mode i cc3 n cke vih(min), cs vih(min), t cc = t cc (min) 510 470 430 ma operating current ( burst mode) i cc4 i ol =0ma , t cc = t cc (min), page burst, all banks activated. 1200 1100 990 ma refresh current i cc5 t rc t rfc 370 350 330 ma 2 self refresh current i cc6 cke 0.2v 7 ma operating current (4bank interleaving) i cc7 burst lenth=4 t rc t rc (min) i ol =0ma, t cc = t cc (min) 1400 1300 1180 ma recommended operating conditions unless otherwise noted, t j =0 to 100 c) controller dram vddq vssq odt of dram input level should be measured at this point - 34 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc ac operating test conditions (v dd =2.5v0.1v, t j = 0 to 100 c) parameter value unit note input reference voltage for ck(for single) 0.50*v ddq v ck and ck signal maximum peak swing 1.5 v ck signal minimum slew rate 1.0 v/ns input levels(v ih /v il )v ref +0.25/v ref -0.25 v input timing measurement reference level v ref v output timing measurement reference level 1/2 v ddq v output load condition see fig.1 output c load =10pf (fig. 1) output load circuit z0=60 ? v ref =0.5*v ddq capacitance (v dd =2.5v, t a = 25 c, f=1mhz) parameter symbol min max unit input capacitance ( ck, ck )c in1 3.0 5 pf input capacitance (a 0 ~a 10 , ba 0 ~ba 1 )c in2 3.0 5 pf input capacitance ( cke, cs , ras ,cas , we ) c in3 3.0 5 pf data & dqs input/output capacitance(dq 0 ~dq 31 )c out 3.0 5 pf input capacitance(dm0 ~ dm3) c in4 3.0 5 pf - 35 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc ac characteristics 1. the cycle to cycle jitter and 2~6 cycle short term jitter. parameter symbol -20 (gf1000) -22 (gf900) -25 (gf800) unit min max min max min max ck cycle time cl=7 tck 2.04.0----ns cl=6 - - 2.22 4.0 - - ns cl=5 - - - - 2.5 4.0 ns ck high width tch 0.45 0.55 0.45 0.55 0.45 0.55 tck ck low width tcl 0.45 0.55 0.45 0.55 0.45 0.55 tck dqs out access time from ck tdqs ck -0.35 0.35 -0.45 0.45 -0.45 0.45 ns data strobe edge to dout edge tdqs q -0.225 0.225 -0.25 0.25 -0.28 0.28 ns read preamble trpre 0.85 1.15 0.88 1.12 0.9 1.1 tck read postamble trpst 0.35 0.65 0.38 0.62 0.4 0.6 tck dqs in/out high level tdqsh 0.45 0.55 0.45 0.55 0.45 0.55 tck dqs in/out low level tdqsl 0. 45 0.55 0.45 0.55 0.45 0.55 tck address and control input setup tis 0.5 - 0.55 - 0.6 - ns address and control input hold tih 0.5 - 0.55 - 0.6 - ns write command to first dqs latching transition tdqss wl - 0.15 wl + 0.15 wl - 0.15 wl + 0.15 wl - 0.15 wl + 0.15 tck write preamble setup time twpres 0 - 0 - 0 - ps write postamble twpst 0.4 0.6 0.4 0.6 0.4 0.6 tck write preamble twpre 0.35 - 0.35 - 0.35 - tck dq_in and dm setup time to dqs tds 0.25 - 0.27 - 0.3 - ns dq_in and dm hold time to dqs tdh 0.25 - 0.27 - 0.3 - ns clock half period thp tcl/h min - tcl/h min - tcl/h min - ns data output hold time from dqs t qh thp-0.225 - thp-0.25 - thp-0.28 - ns jitter over 1-6 clock cycl es of ck tj *1 - 50 - 55 - 65 ps cycle to cycle duty cycle error tdc,err - 50 - 55 - 65 ps rise and fall times of ck tr, tf - 400 - 450 - 500 ps simplified timing @ bl=4, cl=7, al=0 cmd post cas nop nop dq?s ck, ck 02 1 7891011 dout a 0 dout a1 dout a2 dout a3 dqs din a0 din a1 din a2 din a3 read a rl = 7 nop nop nop 6 wdqs nop nop nop post cas write a wl = 1 12 - 36 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc note 1 : - the jedec ddr-ii specification currently def ines the output data valid window(tdv) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - the previously used defini tion of tdv(=0.35tck) artificia lly penalizes system timing budgets by assuming the worst case output valid window even then the clock duty cycle applie d to the device is better than 45/55% - a new ac timing term, tqh which stands for data output hold time from dqs is defined to a ccount for clock duty cycle variation and replaces tdv - tqhmin = thp-x where . thp=minimum half clo ck period for any given cycle and is defined by clock high or cl ock low time(tch,tcl) . x=a frequency dependent timing allowance account for tdqsqmax tqh timing (cl7, bl4) 178 thp ck, ck dqs dq cs 69 01 command reada tqh da0 tdqsq(max) tdqsq(max) da1 da2 da3 - 37 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc ac characteristics (i) note : 1. for normal write operation, ev en numbers of din are to be written inside dram parameter symbol -20 (gf1000) -22 (gf900) -25 (gf800) unit min max min max min max row cycle time trc 22-21-18- tck refresh row cycle time trfc 27 - 25 - 22 - tck row active time tras 15 100k 14 100k 12 100k tck ras to cas delay for read trcdrd 8 - 8 - 7 - tck ras to cas delay for write trcdwr 5 - 5 - 4 - tck row precharge time trp 7 - 7 - 6 - tck row active to row active trrd 5 - 5 - 4 - tck last data in to row precharge twr 5 - 5 - 4 - tck last data in to read command tcdlr 4 - 4 - 4 - tck col. address to col. address tccd 2 - 2 - 2 - tck mode register set cycle time tmrd 4 - 4 - 4 - tck auto precharge write recovery + precharge tdal 12 - 12 - 10 - tck exit self refresh to any command txsa 20000 - 20000 - 20000 - tck power down exit time tpdex 4tck+tis - 4tck+tis - 4tck+tis - ns refresh interval time tref 7.8 - 7.8 - 7.8 - us - 38 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc package dimensions (fbga) unit : mm 13.0 13.0 0.8 0.8 0.25 0.05 1.40 max - 39 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc ibis: i/v characteristics for input and output buffers 1. the typical pulldown v-i curve for ddr sdram devices will be within the inner bounding lines of the v-i curve of figure a. 2. the 30 ohm@odt off variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the v-i curve of figure a. 3. the typical pullup v-i curve for ddr sdram devices will be wi thin the inner bounding lines of the v-i curve of below figure b. 4. the 30 ohm@odt off variation pullup curr ent from minimum to maximum process, te mperature and voltage will lie within the outer bounding lines of the v-i curve of figrue b. 5. the 30 ohm@odt off variation in the ra tio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to vddq/2 6. the 30 ohm@odt off variation in the ratio of the nominal pu llup to pulldown current should be unity 10%, for device drain to source voltages from 0 to vddq/2 30 ohm driver @ odt off maximum typical minumum vout(v) iout(ma) minimum typical maximum iout(ma) figure b : pullup charateristics figure a : pulldown charateristics 0 5 10 15 20 25 30 35 0 0.10.20.30.40.50.60.70.80.9 1 1.11.21.31.41.51.61.71.81.9 vout(v) -35 -30 -25 -20 -15 -10 -5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 the termination resistor of the controller must be set to a appr opriate value to satisfy output voltage level if the odt of dra m is on. - 40 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc temperature (tj) typical 50 c minimum 100 c maximum 0 c vdd/vddq typical 2.5v minimum 2.4v maximum 2.6v the above characteristics are specified under bes t, worst and normal process variation/conditions pulldown current (ma) pullup current (ma) voltage (v) typical minimum maximum typical minimum maximum 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.1 4.4 3.0 6.3 -3.6 -2.5 -4.9 0.2 8.1 5.5 11.8 -6.9 -4.6 -9.3 0.3 11.2 7.6 16.4 -9.7 -6.6 -13.3 0.4 13.8 9.3 20.4 -12.2 -8.2 -17.0 0.5 15.9 10.6 23.5 -14.3 -9.6 -20.1 0.6 17.4 11.5 25.9 -16.1 -10.7 -22.7 0.7 18.4 12.1 27.5 -17.4 -11.6 -24.6 0.8 19.0 12.4 28.4 -18.4 -12.3 -26.0 0.9 19.4 12.6 29.0 -19.1 -12.8 -27.1 1.0 19.7 12.8 29.3 -19.7 -13.2 -28.0 1.1 19.8 12.9 29.5 -20.3 -13.6 -28.7 1.2 20.0 13.0 29.7 -20.7 -13.9 -29.3 1.3 20.1 13.1 29.9 -21.1 -14.2 -29.8 1.4 20.2 13.1 30.0 -21.5 -14.5 -30.3 1.5 20.2 13.2 30.1 -21.8 -14.7 -30.7 1.6 20.3 13.2 30.2 -22.1 -14.9 -31.1 1.7 20.4 13.3 30.3 -22.4 -15.1 -31.4 1.8 20.4 13.3 30.3 -22.6 -15.3 -31.8 1.9 20.5 13.5 30.4 -22.9 -15.5 -32.1 - 41 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc 1. the typical pulldown v-i curve for ddr sdram devices will be within the inner bounding lines of the v-i curve of figure a. 2. the 30 ohm@odt 60 ohm fix variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the v-i curve of figure a. 3. the typical pullup v-i curve for ddr sdram devices will be wi thin the inner bounding lines of the v-i curve of below figure b. 4. the 30 ohm@odt 60 ohm fix variation pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figrue b. 5. the 30 ohm@odt 60 ohm fix variation in the ratio of the ma ximum to minimum pullup and pulldow n current will not exceed 1.7, for device drain to source voltage from 0 to vddq/2 6. the 30 ohm@odt 60 ohm fix variation in the ratio of the nominal pullup to pulldow n current should be unity 10%, for device drain to source voltages from 0 to vddq/2 30 ohm driver @ odt 60 ohm fix. maximum typical minumum vout(v) iout(ma) minimum typical maximum iout(ma) figure b : pullup charateristics figure a : pulldown charateristics vout(v) -20 -10 0 10 20 30 40 50 60 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 -60 -50 -40 -30 -20 -10 0 10 20 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 - 42 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc temperature (tj) typical 50 c minimum 100 c maximum 0 c vdd/vddq typical 2.5v minimum 2.4v maximum 2.6v the above characteristics are specified under bes t, worst and normal process variation/conditions pulldown current (ma) pullup current (ma) voltage (v) typical minimum maximum typical minimum maximum 0.0 -14.4 -11.5 -17.1 14.9 11.9 18.0 0.1 -8.5 -7.1 -9.0 9.7 8.1 11.4 0.2 -3.2 -3.3 -1.8 4.8 4.6 5.1 0.3 1.6 0.2 4.7 0.4 1.3 -0.8 0.4 5.8 3.3 10.4 -3.7 -1.7 -6.2 0.5 9.5 5.9 15.4 -7.4 -4.4 -11.2 0.6 12.7 8.2 19.7 -10.8 -6.9 -15.6 0.7 15.3 10.2 23.1 -13.7 -9.2 -19.4 0.8 17.5 11.9 25.9 -16.4 -11.2 -22.6 0.9 19.6 13.5 28.3 -18.8 -13.2 -25.6 1.0 21.5 15.1 30.5 -21.0 -15.0 -28.3 1.1 23.3 16.6 32.6 -23.2 -16.8 -30.9 1.2 25.1 18.1 34.7 -25.3 -18.5 -33.4 1.3 26.8 19.6 36.7 -27.3 -20.2 -35.8 1.4 28.6 21.0 38.7 -29.4 -21.8 -38.1 1.5 30.3 22.4 40.7 -31.3 -23.5 -40.4 1.6 32.0 23.9 42.7 -33.3 -25.1 -42.7 1.7 33.7 25.3 44.6 -35.2 -26.6 -44.9 1.8 35.4 26.7 46.6 -37.1 -28.2 -47.1 1.9 37.1 28.1 48.5 -39.0 -29.8 -49.3 - 43 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc 1. the typical pulldown v-i curve for ddr sdram devices will be within the inner bounding lines of the v-i curve of figure a. 2. the 30 ohm@odt 120 ohm fix variation in driver pulldown curr ent from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the v-i curve of figure a. 3. the typical pullup v-i curve for ddr sdram devices will be wi thin the inner bounding lines of the v-i curve of below figure b. 4. the 30 ohm@odt 120 ohm fix variation pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figrue b. 5. the 30 ohm@odt 120 ohm fix variation in the ratio of the ma ximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to vddq/2 6. the 30 ohm@odt 120 ohm fix variation in the ratio of the nomi nal pullup to pulldown current should be unity 10%, for devic e drain to source voltages from 0 to vddq/2 30 ohm driver @odt 120 ohm fix. maximum typical minumum vout(v) iout(ma) minimum typical maximum iout(ma) figure b : pullup charateristics figure a : pulldown charateristics vout(v) -10 0 10 20 30 40 50 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 -50 -40 -30 -20 -10 0 10 0 0 . 1 0 . 2 0 . 3 0 . 4 0 . 5 0 . 6 0 . 7 0 . 8 0 . 9 1 1 . 1 1 . 2 1 . 3 1 . 4 1 . 5 1 . 6 1 . 7 1 . 8 1 . 9 - 44 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc temperature (tj) typical 50 c minimum 100 c maximum 0 c vdd/vddq typical 2.5v minimum 2.4v maximum 2.6v the above characteristics are specified under bes t, worst and normal process variation/conditions pulldown current (ma) pullup current (ma) voltage (v) typical minimum maximum typical minimum maximum 0.0 -7.2 -5.8 -8.6 7.6 6.1 9.1 0.1 -2.1 -2.1 -1.4 3.1 2.9 3.4 0.2 2.5 1.1 5.0 -0.9 0.1 -2.0 0.3 6.4 3.9 10.6 -4.6 -2.5 -6.9 0.4 9.8 6.3 15.4 -7.9 -4.9 -11.5 0.5 12.7 8.3 19.5 -10.8 -6.9 -15.5 0.6 15.1 9.9 22.8 -13.4 -8.8 -19.1 0.7 16.9 11.2 25.3 -15.5 -10.3 -21.9 0.8 18.3 12.2 27.2 -17.3 -11.7 -24.3 0.9 19.5 13.1 28.7 -18.9 -12.9 -26.3 1.0 20.6 14.0 30.0 -20.4 -14.1 -28.1 1.1 21.6 14.8 31.2 -21.7 -15.2 -29.7 1.2 22.6 15.6 32.3 -23.0 -16.2 -31.3 1.3 23.5 16.4 33.4 -24.2 -17.2 -32.7 1.4 24.5 17.1 34.5 -25.4 -18.1 -34.2 1.5 25.4 17.9 35.5 -26.6 -19.1 -35.5 1.6 26.3 18.6 36.5 -27.7 -20.0 -36.9 1.7 27.1 19.4 37.6 -28.8 -20.9 -38.2 1.8 28.0 20.1 38.6 -29.9 -21.8 -39.5 1.9 28.9 20.9 39.6 -31.0 -22.7 -40.7 - 45 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc 1. the typical pulldown v-i curve for ddr sdram devices will be within the inner bounding lines of the v-i curve of figure a. 2. the 45 ohm@ odt off variation in driver pulldown current fr om minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the v-i curve of figure a. 3. the typical pullup v-i curve for ddr sdram devices will be wi thin the inner bounding lines of the v-i curve of below figure b. 4. the 45 ohm@odt off variation in driver pullup current fr om minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figrue b. 5. the 45 ohm@odt off variation in the ra tio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to vddq/2 6. the 45 ohm@odt off variation in the ratio of the nominal pu llup to pulldown current should be unity 10%, for device drain to source voltages from 0 to vddq/2 45 ohm @ odt off maximum typical minumum vout(v) iout(ma) minimum typical maximum iout(ma) figure b : pullup charateristics figure a : pulldown charateristics 0 5 10 15 20 25 30 35 0 0.10.20.30.40.50.60.70.80.9 1 1.11.21.31.41.51.61.71.81.9 vout(v) -35 -30 -25 -20 -15 -10 -5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 - 46 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc temperature (tj) typical 50 c minimum 100 c maximum 0 c vdd/vddq typical 2.5v minimum 2.4v maximum 2.6v the above characteristics are specified under bes t, worst and normal process variation/conditions pulldown current (ma) pullup current (ma) voltage (v) typical minimum maximum typical minimum maximum 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.1 2.8 1.9 4.0 -2.2 -1.5 -3.0 0.2 5.2 3.5 7.5 -4.2 -2.8 -5.7 0.3 7.2 4.9 10.5 -6.0 -4.0 -8.2 0.4 8.8 5.9 13.0 -7.5 -5.0 -10.4 0.5 10.1 6.8 15.0 -8.8 -5.9 -12.3 0.6 11.1 7.3 16.5 -9.8 -6.6 -13.9 0.7 11.7 7.7 17.5 -10.6 -7.1 -15.1 0.8 12.1 7.9 18.1 -11.2 -7.5 -15.9 0.9 12.4 8.0 18.4 -11.7 -7.8 -16.6 1.0 12.5 8.1 18.7 -12.1 -8.1 -17.1 1.1 12.6 8.2 18.8 -12.4 -8.3 -17.5 1.2 12.7 8.3 18.9 -12.7 -8.5 -17.9 1.3 12.8 8.3 19.0 -12.9 -8.7 -18.2 1.4 12.8 8.4 19.1 -13.1 -8.8 -18.5 1.5 12.9 8.4 19.2 -13.3 -9.0 -18.8 1.6 12.9 8.4 19.2 -13.5 -9.1 -19.0 1.7 13.0 8.5 19.3 -13.7 -9.2 -19.2 1.8 13.0 8.5 19.3 -13.8 -9.4 -19.4 1.9 13.1 8.6 19.4 -14.0 -9.5 -19.6 - 47 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc 1. the typical pulldown v-i curve for ddr sdram devices will be within the inner bounding lines of the v-i curve of figure a. 2. the 45 ohm@odt 120 ohm fix variation in driver pulldown curr ent from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the v-i curve of figure a. 3. the typical pullup v-i curve for ddr sdram devices will be wi thin the inner bounding lines of the v-i curve of below figure b. 4. the 45 ohm@odt 120 ohm fix variation pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figrue b. 5. the 45 ohm@odt 120 ohm fix variation in the ratio of the ma ximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to vddq/2 6. the 45 ohm@odt 120 ohm fix variation in the ratio of the nomi nal pullup to pulldown current should be unity 10%, for devic e drain to source voltages from 0 to vddq/2 45 ohm driver @odt 120 ohm fix. maximum typical minumum vout(v) iout(ma) minimum typical maximum iout(ma) figure b : pullup charateristics figure a : pulldown charateristics vout(v) -10 -5 0 5 10 15 20 25 30 35 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 -35 -30 -25 -20 -15 -10 -5 0 5 10 0 0 . 1 0 . 2 0 . 3 0 . 4 0 . 5 0 . 6 0 . 7 0 . 8 0 . 9 1 1 . 1 1 . 2 1 . 3 1 . 4 1 . 5 1 . 6 1 . 7 1 . 8 1 . 9 - 48 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc temperature (tj) typical 50 c minimum 100 c maximum 0 c vdd/vddq typical 2.5v minimum 2.4v maximum 2.6v the above characteristics are specified under bes t, worst and normal process variation/conditions pulldown current (ma) pullup current (ma) voltage (v) typical minimum maximum typical minimum maximum 0.0 -7.3 -5.8 -8.6 7.6 6.1 9.2 0.1 -3.7 -3.2 -3.7 4.6 3.9 5.3 0.2 -0.5 -0.9 0.7 1.8 1.9 1.6 0.3 2.4 1.2 4.6 -0.8 0.0 -1.8 0.4 4.8 2.9 8.0 -3.2 -1.7 -4.9 0.5 7.0 4.4 11.0 -5.3 -3.2 -7.8 0.6 8.8 5.7 13.5 -7.1 -4.6 -10.3 0.7 10.2 6.8 15.4 -8.8 -5.8 -12.4 0.8 11.4 7.7 16.9 -10.2 -7.0 -14.2 0.9 12.5 8.6 18.2 -11.5 -8.0 -15.8 1.0 13.5 9.4 19.3 -12.7 -9.0 -17.3 1.1 14.4 10.7 20.5 -13.9 -9.9 -18.6 1.2 15.4 10.9 21.5 -15.0 -10.8 -19.9 1.3 16.3 11.6 22.6 -16.0 -11.7 -21.2 1.4 17.1 12.4 23.6 -17.1 -12.5 -22.4 1.5 18.0 13.1 24.6 -18.1 -13.4 -23.7 1.6 18.9 13.8 25.6 -19.1 -14.2 -24.8 1.7 19.8 14.6 26.6 -20.1 -15.0 -16.0 1.8 20.6 15.3 27.6 -21.1 -15.8 -27.2 1.9 21.5 16.0 28.6 -22.1 -16.7 -28.3 - 49 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc 1. the typical pulldown v-i curve for ddr sdram devices will be within the inner bounding lines of the v-i curve of figure a. 2. the 60 ohm@odt off variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the v-i curve of figure a. 3. the typical pullup v-i curve for ddr sdram devices will be wi thin the inner bounding lines of the v-i curve of below figure b. 4. the 60 ohm@odt off variation in drive pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figrue b. 5. the 60 ohm@odt off variation in the ra tio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to vddq/2 6. the 60 ohm@odt off variation in the ratio of the nominal pu llup to pulldown current should be unity 10%, for device drain to source voltages from 0 to vddq/2 60 ohm @odt off maximum typical minumum vout(v) iout(ma) minimum typical maximum iout(ma) figure b : pullup charateristics figure a : pulldown charateristics vout(v) 0 2 4 6 8 10 12 14 16 0 0.10.20.30.40.50.60.70.80.9 1 1.11.21.31.41.51.61.71.81.9 -16 -14 -12 -10 -8 -6 -4 -2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 - 50 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc temperature (tj) typical 50 c minimum 100 c maximum 0 c vdd/vddq typical 2.5v minimum 2.4v maximum 2.6v the above characteristics are specified under bes t, worst and normal process variation/conditions pulldown current (ma) pullup current (ma) voltage (v) typical minimum maximum typical minimum maximum 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.1 2.0 1.4 2.9 -1.6 -1.1 -2.2 0.2 3.7 2.5 5.4 -3.1 -2.1 -4.2 0.3 5.1 3.5 7.5 -4.4 -2.9 -6.0 0.4 6.3 4.2 9.3 -5.5 -3.7 -7.6 0.5 7.3 4.8 10.7 -6.4 -4.3 -9.0 0.6 7.9 5.2 11.8 -7.2 -4.8 -10.1 0.7 8.4 5.5 12.5 -7.7 -5.2 -11.0 0.8 8.7 5.7 12.9 -8.2 -5.5 -11.6 0.9 8.8 5.8 13.2 -8.5 -5.7 -12.1 1.0 8.9 5.8 13.3 -8.8 -5.9 -12.4 1.1 9.0 5.9 13.4 -9.0 -6.0 -12.7 1.2 9.1 5.9 13.5 -9.2 -6.2 -13.0 1.3 9.1 5.9 13.6 -9.4 -6.3 -13.2 1.4 9.2 6.0 13.6 -9.5 -6.4 -13.5 1.5 9.2 6.0 13.7 -9.7 -6.5 -13.6 1.6 9.2 6.0 13.7 -9.8 -6.6 -13.8 1.7 9.3 6.0 13.8 -9.9 -6.7 -14.0 1.8 9.3 6.1 13.8 -10.1 -6.8 -14.1 1.9 9.3 6.2 13.8 -10.2 -6.9 -14.3 - 51 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc 1. the typical pulldown v-i curve for ddr sdram devices will be within the inner bounding lines of the v-i curve of figure a. 2. the 60 ohm@odt 120 ohm fix variation in driver pulldown curr ent from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the v-i curve of figure a. 3. the typical pullup v-i curve for ddr sdram devices will be wi thin the inner bounding lines of the v-i curve of below figure b. 4. the 60 ohm@odt 120 ohm fix variation in drive pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figrue b. 5. the 60 ohm@odt 120 ohm fix variation in the ratio of the ma ximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to vddq/2 6. the 60 ohm@odt 120 ohm fix variation in the ratio of the nomi nal pullup to pulldown current should be unity 10%, for devic e drain to source voltages from 0 to vddq/2 maximum typical minumum vout(v) iout(ma) minimum typical maximum iout(ma) figure b : pullup charateristics figure a : pulldown charateristics vout(v) 60 ohm driver @odt 120 ohm fix. -10 -5 0 5 10 15 20 25 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 -25 -20 -15 -10 -5 0 5 10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 - 52 - rev. 1.7 (jan. 2003) 128m gddr2 sdram K4N26323AE-gc temperature (tj) typical 50 c minimum 100 c maximum 0 c vdd/vddq typical 2.5v minimum 2.4v maximum 2.6v the above characteristics are specified under bes t, worst and normal process variation/conditions pulldown current (ma) pullup current (ma) voltage (v) typical minimum maximum typical minimum maximum 0.0 -7.3 -5.8 -8.7 7.6 6.1 9.2 0.1 -4.5 -3.7 -4.9 5.2 4.3 6.1 0.2 -2.0 -1.9 -1.4 2.9 2.7 3.2 0.3 0.3 -0.2 1.6 0.8 1.1 0.5 0.4 2.3 1.2 4.3 -1.1 -0.3 -2.1 0.5 4.1 2.5 6.7 -2.9 -1.6 -4.4 0.6 5.6 3.6 8.7 -4.5 -2.8 -6.5 0.7 6.9 4.6 10.4 -5.9 -3.9 -8.3 0.8 8.0 5.5 11.7 -7.1 -4.9 -9.9 0.9 9.0 6.3 12.9 -8.3 -5.9 -11.3 1.0 9.9 7.0 14.0 -9.4 -6.8 -12.6 1.1 10.8 7.8 15.1 -10.5 -7.6 -13.9 1.2 11.7 8.5 16.1 -11.5 -8.5 -15.1 1.3 12.6 9.3 17.1 -12.5 -9.3 -16.3 1.4 13.5 10.0 18.1 -13.5 -10.1 -17.4 1.5 14.2 10.7 19.1 -14.5 -10.9 -18.5 1.6 15.2 11.4 20.1 -15.5 -11.7 -19.7 1.7 16.1 12.1 21.1 -16.4 -12.5 -20.8 1.8 16.9 12.8 22.1 -17.4 -13.3 -21.0 1.9 17.8 13.6 23.1 -18.3 -14.1 -23.0 |
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